Integrated capacitor device and method of fabricating the same

ABSTRACT

A method of fabricating a semiconductor device comprises the steps of forming an insulating layer on a semiconductor substrate including a first layer, forming a through hole in the insulating layer so as to reach for the first layer, charging an oxide dielectric substance into the through hole to form an oxide dielectric section therein, and forming a second layer on the oxide dielectric section.

TECHNICAL FIELD

The present invention relates to a semiconductor device having oxidedielectrics, and also relates to a method of fabricating thesemiconductor device.

BACKGROUND ART

A memory device incorporating a related ferroelectric condenser is knownin the field of semiconductor devices having oxide dielectrics. Thisrelated ferroelectric condenser is composed such that a ferroelectric,which is a type of oxide dielectric, is interposed between an upper anda lower electrode. FIGS. 7A to 8B are cross-sectional views showing arelated method of fabricating the related ferroelectric condenser usedin the above-described memory device.

During fabrication of the related ferroelectric condenser, as shown inFIG. 7A, an insulating film 4 is formed on a substrate 2 having CMOS andother elements (not shown). A platinum layer 6 is then formed bydepositing platinum on the insulating film 4 by means of sputtering. Inthe same manner, as shown in FIGS. 7B to 7C, a ferroelectric layer 8 andthen a platinum layer 10 are formed on the platinum layer 6.

Next, as shown in FIG. 8A, an upper electrode 12 is formed by conductingRIE (Reactive Ion Etching) on the platinum layer 10, using a resist as amask. In the same manner, as shown in FIGS. 8B to 8C, etching issuccessively conducted on the ferroelectric layer 8 and the platinumlayer 6 using another resist (not shown) as a mask, so that aferroelectric section 14 and a lower electrode 16 can be formed.Finally, an insulating film (not shown) is formed to cover the substrate2.

However, problems associated with RIE etching may be encountered duringfabrication of the related ferroelectric condenser. That is, theferroelectric section 14 is formed by conducting RIE etching on thedeposited ferroelectric layer 8. The RIE etching causes ions to shockthe ferroelectric section 14, resulting in the ferroelectric section 14having a tendency to develop a lattice defect. There is also a tendencyfor the RIE etching to cause a reducing reaction in the ferroelectricsection 14. Accordingly, ferroelectricity, which is a function of theferroelectric section 14, tends to deteriorate. These problems areespecially serious in the case of a highly integrated memory device inwhich the area of the ferroelectric section 14 is small.

It is an object of the present invention to overcome the above-describedproblems by providing a semiconductor device characterized in that anoperation of the oxide dielectric section (e.g., a ferroelectric) isseldom deteriorated. It is a further object of the present invention toprovide a method of fabricating the semiconductor device.

In the related method of fabricating the related ferroelectriccondenser, the following problems may be encountered. In order toprevent a product of etching (i.e., a side wall polymer), which isdifficult to be removed, from adhering to a side 14 a of theferroelectric section 14 when RIE etching is conducted on theferroelectric layer 8, a ratio of isotropic etching is set at a highvalue. Accordingly, the side face 14 a of the ferroelectric section 14is greatly inclined. This inclination results in the area required forthe ferroelectric section 14 to be unnecessarily increased, which inturn obstructs the enhancement of the degree of integration of thesemiconductor device into which the ferroelectric condenser isincorporated.

Further, when consideration is given to the fluctuation of the etchingcondition, it is necessary to provide a large margin between theferroelectric section 14 and the upper electrode 12, or between theferroelectric section 14 and the lower electrode 16.

It is another object of the present invention to solve the aboveproblems by providing a semiconductor device having a degree ofintegration that can be easily enhanced. It is a further object of thepresent invention to provide a method of fabricating such asemiconductor device.

DISCLOSURE OF THE INVENTION

In the first aspect of the present invention, there is provided a methodof fabricating a semiconductor device comprising the steps of: formingan insulating layer on a semiconductor substrate including a firstlayer; forming a through hole in the insulating layer so as to reach forthe first layer; charging an oxide dielectric substance into the throughhole to form an oxide dielectric section therein; and forming a secondlayer on the oxide dielectric section.

When an oxide dielectric substance is charged into the through hole, theoxide dielectric section, having the same shape as the internal shape ofthe through hole, is formed. Thus, the oxide dielectric section can beformed into a predetermined shape without etching. It is thereforepossible to avoid the occurrence of a lattice defect and a reducingreaction, which are caused by etching the oxide dielectric section. As aresult, the function of the oxide dielectric section is seldomdeteriorated.

When the shape of the through hole is determined, the shape of the oxidedielectric section is thus determined. Accordingly, as compared with acase in which the shape of the oxide dielectric section is determined byetching, fluctuation of the shape of the oxide dielectric section isreduced. Therefore, it is possible to reduce a margin for absorbing thefluctuation and enhance a grade of integration of the device.

When the shape of the through hole is determined, a contact area betweenthe first layer and the oxide dielectric section is thus determined.Accordingly, fluctuation of the contact area is reduced. In case it isconstituted a condenser wherein the first layer serves as a lowerelectrode, capacity fluctuation thereof can be reduced.

In this connection, a method of forming the through hole in theinsulating layer is not particularly restricted. For example, even whenthe well-known etching method is applied, the through hole can be formedwith sufficiently high accuracy.

In the second aspect of the present invention, the method furthercomprises forming the first layer on an upper surface of thesemiconductor substrate.

In the third aspect of the present invention the step of forming theoxide dielectric section includes the steps of laminating the oxidedielectric substance onto the insulating layer while filling the throughhole therewith and removing the oxide dielectric substance located areasother than the inside of the through hole.

For example, the step of laminating the oxide dielectric substance isconducted by the sol-gel method and the step of removing the substanceis conducted by the CMP (chemical mechanical polishing) method.Accordingly, the oxide dielectric section can be formed with significantease.

In the fourth aspect of the present invention, the method furthercomprises the step of patterning the first layer before the step offorming the insulating layer.

Accordingly, in a process in which a layer arranged above the firstlayer (e.g., the second layer) is patterned by the etching, it is notnecessary to conduct a patterning of the first layer lying in thelowermost. That is, in the above step of patterning, it is not necessaryto etch deeply. Therefore, irregularities on the upper surface of thedevice are not so remarkable and can be flattened thereby.

In the fifth aspect of the present invention, the method furthercomprises the step of planarizing an upper surface of the insulatinglayer before the step of filling the through hole with the oxidedielectric substance.

Accordingly, when the oxide dielectric substance placed outside of thethrough hole is removed by, for example, the CMP method, the oxidedielectric substance can be easily and positively removed therefrom.

In the sixth aspect of the present invention, the method furthercomprises the step of patterning the first layer after the dielectricoxide dielectric section is formed.

Accordingly, in the step of forming the oxide dielectric section, thefirst layer has not been patterned yet, and the insulating layer formedon the first layer is flat. Therefore, when the oxide dielectricsubstrate placed outside of the through hole is removed by, for example,the CMP method, the oxide dielectric substance can be easily andpositively removed therefrom.

In the seventh aspect of the present invention, the method furthercomprises the step of patterning the second layer so as to cover entireupper surface of the oxide dielectric substance.

Accordingly, even when the patterning is conducted by the etching, theoxide dielectric section is not affected by the etching. It is thereforepossible to avoid the occurrence of a lattice defect and a reducingreaction, which are caused by the patterning of the second layer. As aresult, the function of the oxide dielectric section is seldomdeteriorated.

When the shape of the through hole is determined, a contact area betweenthe second layer and the oxide dielectric section is thus determined.Accordingly, fluctuation of the contact area is reduced. In case it isconstituted a condenser wherein the second layer serves as an upperelectrode, capacity fluctuation thereof can be reduced.

In the eighth aspect of the present invention, an inner circumferencialwall of the through hole and the insulating layer make an angle of 80-90degree.

Accordingly, in case it is constituted a condenser wherein the firstlayer serves as a lower electrode and the second layer serves as anupper electrode, such condenser having a predetermined capacity can berealized with a minimum projected plan area.

In the ninth aspect of the present invention, the step of forming thefirst layer includes the step of forming a first electrode on the uppersurface of the semiconductor substrate in which a circuit element isformed.

In the tenth aspect of the present invention, the first layer is animpurity diffusion area formed on the upper surface of the semiconductorsubstrate.

Accordingly, a condenser having high reliability can be formed on thesemiconductor substrate in which any desired circuit element is formed.

Further, since it is not necessary to conduct a patterning of the oxidedielectric substrate, deterioration of any circuit element arranged inlower layer can be reduced. Particularly, in case the first layer is animpurity diffusion area such as a drain or a source of a transistor,such deterioration of any circuit element arranged in the lower layer isreduced.

In the eleventh aspect of the present invention, the first layerincludes a platinum layer.

In the twelfth aspect of the present invention, the first layer includesan iridium layer.

In the thirteenth aspect of the present invention, the first layer istwo-layers film constituted by a lower layer made of platinum and anupper layer made of IrO₂.

In the fourteenth aspect of the present invention, the step of formingthe through hole is conducted by RIE.

Accordingly, the through hole, the inner circumferencial wall of whichis perpendicular to the first layer, can be easily formed with highaccuracy.

In the fifteenth aspect of the present invention, the step ofplanarizing the upper surface of the insulating layer includes the stepsof forming a SOG layer so as to fill recesses formed on the uppersurface of the insulating layer by the SOG method and etching back anupper portion thereof.

In the sixteenth aspect of the present invention, the step of laminatingthe oxide dielectric substance is conducted by the sol-gel method andthe step of removing the substance is conducted by the etching-back.

In the seventeenth aspect of the present invention, the step oflaminating the oxide dielectric substance is conducted by the sputteringmethod and the step of removing the substance is conducted by the CMPmethod.

According to any one of the fifteenth to seventeenth aspects of thepresent invention, an accurate condenser having less fluctuation ofcapacity can be easily realized without damaging any lower layer.

In the eighteenth aspect of the present invention, there is provided asemiconductor device comprising: a first layer formed on an uppersurface of a semiconductor substrate; an oxide dielectric section formedon the first layer, an outer peripheral side face of which is surroundedby an insulating layer such that the outer peripheral side face and theinsulating layer make an angle of 80-90 degree; and a second layer isformed on the oxide dielectric section.

Accordingly, in case it is constituted a condenser wherein the firstlayer serves as a lower electrode and the second layer serves as anupper electrode, such condenser having a predetermined capacity can berealized with a minimum projected plan area. As a result, a devicehaving a high grade of integration can be realized.

In the nineteenth aspect of the present invention, the first layer is anelectrode including a platinum layer, and the first and second layerssandwich the insulating layer and the oxide dielectric sectiontherebetween.

In the twentieth aspect of the present invention, the first layer istwo-layers film constituted by a lower layer made of platinum and anupper layer made of IrO₂.

In the twenty-first aspect of the present invention, the oxidedielectric section is made of selected one of PZT, SBT and PLZT, and anferroelectric condenser is constituted by the first and second layersand the oxide dielectric section.

In the twenty-second aspect of the present invention, the first layer isone of a source layer and a drain layer of a transistor, and anferroelectric condenser is constituted by the first and second layersand the oxide dielectric section.

According to any one of the twentieth to twenty-second aspects of thepresent invention, a semiconductor device having high reliability andaccuracy can be realized.

In this connection, hereinafter, “to form the first layer on thesemiconductor substrate” or “to provide the first layer on thesemiconductor substrate” is a concept including the following threecases. The first case is that the first layer is formed coming intocontact with the semiconductor substrate. The second case is that thefirst layer is formed on at least one another layer such as aninsulating layer, which has already been formed on the semiconductorsubstrate. The third case is that the semiconductor substrate itself ifthe first layer.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A to 1C are cross-sectional views of a ferroelectric condenserfor explaining a method of fabricating a ferroelectric condenser sectionaccording to a first embodiment of the present invention, wherein theseviews respectively show the primary fabrication process;

FIGS. 2A to 2C are cross-sectional views of a ferroelectric condenserfor explaining the method of fabricating the ferroelectric condensersection according to the first embodiment of the present invention,wherein these views respectively show the primary fabrication process;

FIGS. 3A to 3C are cross-sectional views of a ferroelectric condenserfor explaining the method of fabricating the ferroelectric condensersection according to the first embodiment of the present invention,wherein these views respectively show the primary fabrication process;

FIGS. 4A to 4C are cross-sectional views of a ferroelectric condenserfor explaining a method of fabricating the ferroelectric condensersection according to a second embodiment of the present invention,wherein these views respectively show the primary fabrication process;

FIGS. 5A to 5C are cross-sectional views of a ferroelectric condenserfor explaining the method of fabricating the ferroelectric condensersection according to the second embodiment of the present invention,wherein these views respectively show the primary fabrication process;

FIGS. 6A and 6B are cross-sectional views of a ferroelectric condenserfor explaining the method of fabricating the ferroelectric condensersection according to the second embodiment of the present invention,wherein these views respectively show the primary fabrication process;

FIGS. 7A to 7C are cross-sectional views of a related ferroelectriccondenser for explaining a related method of fabricating a ferroelectriccondenser section, wherein these views respectively show the primaryfabrication process; and

FIGS. 8A to 8C are cross-sectional views of a related ferroelectriccondenser for explaining the related method of fabricating aferroelectric condenser section, wherein these views respectively showthe primary fabrication process.

BEST MODE FOR CARRYING OUT THE INVENTION

The structure of a ferroelectric condenser, which is a portion of amemory device of a semiconductor device according to a first embodimentof the present invention, will first be explained. FIGS. 1A to 3C arecross-sectional views of the ferroelectric condenser of the memorydevice for explaining a method of fabricating the ferroelectriccondenser section according to this first embodiment, wherein theseviews respectively show the primary fabricating process.

As shown in FIG. 3C, a ferroelectric condenser Cf is formed on aninsulating film 24 that is provided on a substrate (not shown). Theferroelectric condenser Cf includes a lower electrode (first layer) 27,a ferroelectric section (oxide dielectric section) 31 and an upperelectrode (second layer) 33, wherein the layers are placed in thisorder. An insulating film 34 is formed on the ferroelectric condenserCf.

A side face 31 a of the ferroelectric section 31 is formed in such amanner that it is substantially perpendicular to the ferroelectricsection 31 concerned. An insulating film (insulating layer) 28 is formedto surround the side face 31 a. A portion of this insulating film 28 andthe ferroelectric section 31 are interposed between the lower electrode27 and the upper electrode 33. Accordingly, it is possible to realize aferroelectric condenser Cf having a predetermined capacity and occupyinga minimum projected plan area. It is therefore further possible toobtain a memory device having a high grade of integration.

Referring to FIGS. 1A to 3C, a method of fabricating the ferroelectriccondenser Cf will now be explained. As shown in FIG. 1A, a substrate 22,having CMOS and other elements (not shown), is provided. An insulatingfilm 24 composed of BPSG (boro-phospho-silicate-glass) is formed on theCMOS elements. When platinum is deposited on the insulating film 24 bymeans of, for example, sputtering, a platinum layer 26 is formed. Inthis connection, it is preferable that an upper surface of theinsulating film 24 is previously flattened using a method such as reflowor CMP.

Next, as shown in FIG. 1B, a lower electrode 27 is formed into apredetermined shape by subjecting the platinum layer 26 to patterning.Patterning of the platinum layer 26 is conducted by forming a resistlayer of a predetermined shape (not shown) on the upper surface of theplatinum layer 26, and then etching the platinum layer 26 by RIE, usingthe resist layer as a mask.

Next, as shown in FIG. 1C, the insulating film (insulating layer) 28 isformed so that the lower electrode 27 and the insulating film 24 arecovered with the insulating film 28. The insulating film 28 is formed,for example, when silicon oxide is deposited by the CVD method (ChemicalVapor Deposition). In this embodiment, an upper surface of the depositedinsulating film 28 is flattened.

The upper surface of the insulating film 28 may be flattened by any oneof a number of methods. For example, a SOG (Spin On Glass) layer (notshown) may be formed on the insulating layer 28, so that irregularitieson the upper surface of the insulating film 28 are filled, and the upperportion of the SOG layer then subjected to etchback. Alternatively, theupper surface of the insulating film 28 may be flattened using the CMPmethod.

Next, as shown in FIG. 2A, a through hole 28 a, which reaches the lowerelectrode 27, is formed in the insulating film 28. The through hole 28 ais formed by placing a resist layer of a predetermined shape (not shown)on the upper surface of the insulating film 28, and then etching theinsulating film 28 by the RIE method, using the resist layer as a mask.

The ferroelectric layer 30 is then formed as shown in FIG. 2B. Morespecifically, a ferroelectric substance (oxide dielectric substance)composed of PZT is laid in the through hole 28 a and on the insulatingfilm 28 by the sol-gel method, the CVD method or sputtering. Due to theforegoing, the ferroelectric substance can be charged into the throughhole 28 a.

Next, as shown in FIG. 2C, the ferroelectric section (oxide dielectricsection) 31 is formed by removing portions of the ferroelectric layer 30that are located in areas other than the inside of the through hole 28a. This removal process may be accomplished using one of a number ofmethods. For example, the CMP method may be solely used. Alternatively,the upper portion of the ferroelectric layer 30 may be partially removedby etchback, and then finishing conducted by the CMP method.

When the upper surface of the insulating film 28 is flattened before theformation of the ferroelectric layer 30 as described above, the portionsof the ferroelectric layer 30 that are located outside the through hole28 a can be easily and positively removed by the CMP method or etchback.

A contact area of the lower electrode 27 with the ferroelectric section31 is determined by an opening area of the lower portion of the throughhole 28 a. Accordingly, fluctuation of the contact area is small. It istherefore possible to reduce fluctuation in the capacity of theferroelectric condenser Cf shown in FIG. 3C.

Next, as shown in FIG. 3A, the platinum layer 32 is formed on theferroelectric section 31 and the insulating film 28 when platinum isdeposited by means of sputtering.

As shown in FIG. 3B, the upper electrode 33 is formed into apredetermined shape by subjecting the platinum layer 32 to patterning.Patterning of the platinum layer 32 is conducted by forming a resistlayer of a predetermined shape (not shown) on the platinum layer 32 andthen etching the platinum layer 32 by RIE, using the resist layer as amask.

Before the upper electrode 33 is formed, the lower electrode 27 hasalready been formed as shown in FIG. 1B. Accordingly, during the processin which the upper electrode 33 is formed by etching the platinum layer32 as shown in FIG. 3B, it is unnecessary to cut the platinum layer 26(shown in FIG. 1A). In other words, it is unnecessary to dig down deeplyin the etching process. Accordingly, irregularities on the upper surfaceof the device are not so remarkable. For the above reasons, the uppersurface of the device can be easily flattened as shown in FIG. 3C.

As shown in FIG. 3B, the upper electrode 33 is formed so that it coversthe overall upper surface of the ferroelectric section 31. Accordingly,when the upper electrode 33 is formed by etching, the ferroelectricsection 31 does not suffer from a lattice defect or a reducing reaction,which are caused by etching.

A contact area of the ferroelectric section 31 with the upper electrode33 is determined by an opening area of the upper portion of the throughhole 28 a. Accordingly, fluctuation of the contact area is small, and itis therefore possible to reduce fluctuation in the capacity offerroelectric condenser Cf.

Finally, as shown in FIG. 3C, the insulating film 34 is formed to coverthe upper electrode 33 and the insulating film 28. The insulating film34 is formed, for example, by depositing silicon oxide using the CVDmethod.

When a ferroelectric substance is charged into the through hole 28 a,the ferroelectric section 31, having the same shape as the internalshape of the through hole 28 a, is formed. Thus, the ferroelectricsection 31 can be formed into a predetermined shape without etching. Itis therefore possible to avoid the occurrence of a lattice defect and areducing reaction, which are caused by etching the ferroelectric section31. As a result, the function of the ferroelectric section 31 is seldomdeteriorated.

When the shape of the through hole 28 a is determined, the shape of theferroelectric section 31 is thus determined. Accordingly, as comparedwith a case in which the shape of the ferroelectric section 31 isdetermined by etching, fluctuation of the shape of the ferroelectricsection 31 is reduced. Therefore, it is possible to reduce a margin forabsorbing the fluctuation and enhance a grade of integration of thedevice.

In the above embodiment, the upper surface of the insulating layer 28 isflattened before the formation of the through hole 28 a. However, in thecase where irregularities on the upper surface of the insulating layer28 are not so remarkable, the process of flattening the upper surface ofthe insulating layer may be omitted.

A method of fabricating a ferroelectric condenser according to a secondembodiment of the present invention will now be explained with referenceto FIGS. 4A to 6B.

First, as shown in FIG. 4A, a substrate 42, having CMOS and otherelements (not shown), is provided. An insulating film 44 composed ofBPSG is formed on the CMOS elements. When platinum is deposited on theinsulating film 44 by means of, for example, sputtering, a platinumlayer (first layer) 46 is formed. In this connection, in the same manneras that of the aforementioned first embodiment, it is preferable that anupper surface of the insulating film 44 be previously flattened using amethod such as reflow or CMP.

Next, as shown in FIG. 4B, an insulating film (insulating layer) 48 isformed on the platinum layer 46. The insulating layer 48 is formed, forexample, by depositing silicon oxide using the CVD method. In thisembodiment, the platinum layer 46 has not yet been subjected topatterning, and therefore, irregularities on the insulating layer 48formed on the platinum layer 46 are not remarkable. Accordingly, unlikethe aforementioned first embodiment, it is unnecessary to flatten theupper surface of the insulating film 48.

Next, as shown in FIG. 4C, a through hole 48 a, which reaches theplatinum layer 46, is formed on the insulating film 48. The through hole48 a is formed by placing a resist layer of a predetermined shape (notshown) on the upper surface of the insulating film 48, and then etchingthe insulating film 48 by the RIE method, using the resist layer as amask.

Next, as shown in FIG. 5A, a ferroelectric layer 50 is formed. When theferroelectric layer 50 is formed, a ferroelectric substance (oxidedielectric substance) composed of PZT is laid in the through hole 48 aand on the insulating film 48 by the sol-gel method, the CVD method orsputtering. Due to the foregoing, the ferroelectric substance can becharged into the through hole 48 a.

Next, as shown in FIG. 5B, a ferroelectric section (oxide dielectricsection) 51 is formed by removing portions of the ferroelectric layer 50that are located in areas other than the inside of the through-hole 48a. This removal process may be accomplished using any one of a number ofmethods. For example, the CMP method may be used solely. Alternatively,the upper portion of the ferroelectric layer 50 may be somewhat removedby etchback, and then finishing conducted by the CMP method.

As described above, irregularities on the upper surface of theinsulating film 48 are not remarkable even if the flattening processingis not conducted. Therefore, portions of the ferroelectric layer 50located outside the through hole 48 a can be easily and positivelyremoved.

Next, a platinum layer (second layer) 52 is formed by depositingplatinum on the ferroelectric section 51 and the insulating film 48 bymeans of sputtering as shown in FIG. 5C. When the platinum layer 52,insulating film 48 and platinum layer 46 are subjected to patterning ofa predetermined shape as shown in FIG. 6A, an upper electrode 53 and alower electrode 47 are formed. For example, when patterning is conductedby RIE, etching may be respectively conducted on the platinum layer 52,insulating film 48 and platinum layer 46 using different types of resist(not shown). Alternatively, etching may be conducted all at once on thethree layers using only one type of resist (not shown).

Finally, as shown in FIG. 6B, the insulating film 54 is formed to coverthe upper electrode 53 and the insulating film 44. The insulating film54 is formed, for example, by depositing silicon oxide using the CVDmethod.

In each embodiment described above, the second layer 33, 52 is cut to asize so that it covers the overall upper surface of the oxide dielectricsection. However, it is possible to cut the second layer to a size sothat a portion of the oxide dielectric section is not covered thereby.

Further, in each embodiment described above, the inner circumferentialwall of the through hole is formed to be perpendicular to the insulatinglayer. However, it is possible to arrange the inner circumferential wallof the through hole in such a manner that it is not perpendicular to theinsulating layer.

Even further, in each embodiment described above, the upper and lowerelectrodes are made of platinum. However, it should be noted thatmaterial of the upper and lower electrodes is not limited to platinum.For example, iridium or iridium oxide may be used for the upper andlower electrodes. Alternatively, not less than two conductor layers maybe used to form the upper and the lower electrodes. For example, eachone of combinations of Pt/IrO₂, Pt/RuO₂, Ir/IrO₂ or the like isapplicable for the upper and lower electrodes.

The first and the second layers are composed of electrically conductivelayers. However, it should be noted that the first and the second layersare not restricted to the above electrically conductive layers. Forexample, when the first or the second layer is composed of asemiconductor or an insulator, it is possible to apply the presentinvention. As a specific example, it is possible to apply the presentinvention to a structure in which a ferroelectric body is laid on asemiconductor substrate, and an upper electrode is placed on theferroelectric body. In this case, a portion of the semiconductorsubstrate or the entire semiconductor substrate composes the firstlayer.

In each embodiment described above, PZT is used as the ferroelectricsubstance. However, it should be noted that the ferroelectric substanceis not limited to the above specific material; for example, it ispossible to use SBT or PLZT.

Further, the oxide dielectric substance is made of a ferroelectricsubstance. However, it should be noted that present invention is notlimited to the above specific example. The present invention can beapplied to any oxide having dielectricity.

It is possible to laminate not less than two oxide dielectric layers tocompose one oxide dielectric layer.

In each embodiment described above, the semiconductor device is composedof a memory device. However, it should be noted that the presentinvention is not restricted to the above specific example. It ispossible to apply the present invention to any semiconductor device.

INDUSTRIAL APPLICABILITY

As has been described heretofore that according to the presentinvention, there can be provided a semiconductor device and a method offabricating the same, wherein a function of an oxide dielectric section,such as ferroelectric, is seldom deteriorated.

Furthermore, there can be provided a semiconductor device having aneasily enhanced degree of integration, and a method of fabricating thesame.

What is claimed is:
 1. A method of fabricating a semiconductor devicecomprising the steps of: forming an insulating layer on a semiconductorsubstrate including a first conductive layer; forming a through hole inthe insulating layer to the first conductive layer; laminating an oxidedielectric substance onto the insulating layer while filing the throughhole therewith to form an oxide dielectric section therein; removing theoxide dielectric substance such that an upper face of the oxidedielectric section and an upper face of the insulating layer are madeflush; and forming a second conductive layer such that a bottom facethereof is brought into contact with the upper faces of the oxidedielectric section and the insulating layer.
 2. The method offabricating a semiconductor device as set forth in claim 1 furthercomprising: forming the first conductive layer on an upper surface ofthe semiconductor substrate.
 3. The method of fabricating asemiconductor device as set forth in claim 2 further comprising thesteps of: patterning the first conductive layer before the step offorming the insulating layer.
 4. The method of fabricating asemiconductor device as set forth in claim 1 further comprising the stepof: planarizing an upper surface of the insulating layer before the stepof filling the through hole with the oxide dielectric substance.
 5. Themethod of fabricating a semiconductor device as set forth in claim 2further comprising the step of: patterning the first conductive layerafter the dielectric oxide dielectric section is formed.
 6. The methodof fabricating a semiconductor device as set forth in claim 1, 2, 3 or4, further comprising the step of: patterning the second conductivelayer so as to cover the entire upper surface of the oxide dielectricsubstance.
 7. The method of fabricating a semiconductor device as setforth in claim 1, 2, 3 or 4, wherein an inner circumferential wall ofthe through hole and the insulating layer are angled relative to thevertical.
 8. The method of fabricating a semiconductor device as setforth in claim 2, wherein the step of forming the first conductive layerincludes the step of forming a first electrode on the upper surface ofthe semiconductor substrate in which a circuit element is formed.
 9. Themethod of fabricating a semiconductor device as set forth in claim 1, 2,3 or 4, wherein the first conductive layer is an impurity diffusion areaformed on the upper surface of the semiconductor substrate.
 10. Themethod of fabricating a semiconductor device as set forth in claim 1, 2,3 or 4, wherein the first conductive layer includes a platinum layer.11. The method of fabricating a semiconductor device as set forth inclaim 1, 2, 3 or 4, wherein the first conductive layer includes aniridium layer.
 12. The method of fabricating a semiconductor device asset forth in claim 1, 2, 3 or 4, wherein the first conductive layer is atwo-layer film including a lower layer made of platinum and an upperlayer made of IrO₂.
 13. The method of fabricating a semiconductor deviceas set forth in claim 7, wherein the step of forming the through hole isconducted by RIE.
 14. The method of fabricating a semiconductor deviceas set forth in claim 4, wherein the step of planarizing the uppersurface of the insulating layer includes the steps of forming a SOGlayer so as to fill recesses formed on the upper surface of theinsulating layer by the SOG method and etching back an upper portionthereof.
 15. The method of fabricating a semiconductor device as setforth in claim 4 or 14, wherein the step of laminating the oxidedielectric substance is conducted by the sol-gel method and the step ofremoving the substance is conducted by the etching-back.
 16. The methodof fabricating a semiconductor device as set forth in claim 4 or 14,wherein the step of laminating the oxide dielectric substance isconducted by the sputtering method and the step of removing thesubstance is conducted by the CMP method.
 17. A semiconductor devicecomprising: a first conductive layer formed on an upper surface of asemiconductor substrate; an oxide dielectric section formed on the firstconductive layer, an outer peripheral side face of which is surroundedby an insulating layer such that an upper face thereof is made flushwith an upper face of the oxide dielectric section; and a secondconductive layer, a lower face of which is brought into contact with theupper faces of the insulating layer and the oxide dielectric section.18. The semiconductor device as set forth in claim 17, wherein the firstconductive layer is an electrode including a platinum layer, and thefirst and second conductive layers sandwich the insulating layer betweenouter portions thereof.
 19. The semiconductor device as set forth claim18, wherein the first conductive layer includes a lower layer made ofplatinum and an upper layer made of IrO₂.
 20. The semiconductor deviceas set forth in claim 18, wherein the oxide dielectric section is formedof one of PZT, SBT and PLZT, and a ferroelectric capacitor is formed bythe first and second conductive layers and the oxide dielectric section.21. The semiconductor device as set forth in claim 17, wherein the firstlayer is one of a source and a drain of a transistor, and aferroelectric capacitor is formed of the first and second conductivelayers and the oxide dielectric section.